Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study

Authors:
Hsiu-Ming Sherman Chang;Kuan-Yu Lin;Kwang-Ting Tim Cheng
Affiliations:
Electrical and Computer Engineering Department, University of California, Santa Barbara, USA 93111;SoC Technology Center, Industrial Technology Research Institute, HsinChu, Taiwan;Electrical and Computer Engineering Department, University of California, Santa Barbara, USA 93111
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2010

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Abstract

Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often takes a long time--in the order of hundreds of milliseconds or even minutes. As testing such devices would require completion of the calibration process first, lengthy calibration would result in unacceptably long testing time. In this paper, we propose techniques to reduce the calibration time in a production testing environment, thereby reduce the overall testing time for the digitally-calibrated designs. In particular, we propose DfT modifications to accelerate the underlying adaptation algorithms and to terminate the calibration process as soon as it reaches convergence. We discuss the applicability of our techniques to general digitally-calibrated designs and illustrate the details using a case study of a digitally-calibrated pipelined ADC. Simulation results show that, for the target ADC, the proposed technique can achieve, on average, 99.5% reduction in the calibration time, which, in turn, results in a 75% reduction in production test time assuming a typical 300-millisecond testing time for testing the specifications of a calibrated ADC.