A Built-in self-calibration scheme for pipelined ADCs

Authors:
Hsiu-Ming Chang;Kuan-Yu Lin;Chin-Hsuan Chen;Kwang-Ting Cheng
Affiliations:
Department of Electrical and Computer Engineering, University of California, Santa Barbara, U.S.A.;Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan;Department of Electrical and Computer Engineering, University of California, Santa Barbara, U.S.A.;Department of Electrical and Computer Engineering, University of California, Santa Barbara, U.S.A.
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

Citing 0
Cited 2

Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study

Journal of Electronic Testing: Theory and Applications
Iterative built-in testing and tuning of mixed-signal/RF systems

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design

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Abstract

There is a strong demand for both calibrating and testing the ADC performance before and after packaging for mixed-signal SoCs and SiPs. In this paper, we propose a built-in self-calibration scheme that offers digitally-controlled calibration of a pipelined ADC without using external stimulus. We further propose a self-testing strategy that uses the effective number of bits (ENOB) derived directly from the steady-state error of the self-calibration process for go/no-go testing as well as for performance binning. This testing process will not incur any additional test time beyond that required for calibration.