A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
BIST for D/A and A/D Converters
IEEE Design & Test
Proceedings of the IEEE International Test Conference
HABIST: Histogram-Based Analog Built-In Self-Test
Proceedings of the IEEE International Test Conference
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
A New Approach for Nonlinearity Test of ADCs/DACs and its Application for BIST
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Testing Digital to Analog Converters based on Oscillation-Test Strategy using Sigma-delta Modulation
ICCD '98 Proceedings of the International Conference on Computer Design
An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters
ATS '01 Proceedings of the 10th Asian Test Symposium
A Built-in-Self-Test Scheme for Digital to Analog Converters
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
On chip testing data converters using static parameters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Design of Linearity Built-in Self-Test for Current-Steering DAC
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in segmented and binary weighted digital to analog converters (DACs). The BIST scheme comprises of a hierarchy of tests including tests for non-monotonicity, checks to detect if the DNL/INL errors exceed 卤0.5 LSB and actual estimation of the DNL/INL. The BIST scheme has been experimentally verified on 10-bit segmented current steering DAC. The DAC, along with the additional circuits required for testing, was designed and fabricated using a 0.35 驴m process. Both simulation and experimental results are included in this paper. Errors estimated using the BIST scheme match well with measurements done on the fabricated device.