A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Testing Digital to Analog Converters based on Oscillation-Test Strategy using Sigma-delta Modulation
ICCD '98 Proceedings of the International Conference on Computer Design
A Built-in-Self-Test Scheme for Digital to Analog Converters
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Static and Dynamic Performance Limitations for High Speed D/a Converters (Kluwer International Series in Engineering and Computer Science, Secs 761.)
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs
Journal of Electronic Testing: Theory and Applications
On chip testing data converters using static parameters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital-Compatible Testing Scheme for Operational Amplifier
Journal of Electronic Testing: Theory and Applications
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In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.