CMOS: mixed-signal circuit design
CMOS: mixed-signal circuit design
Structural Fault Based Specification Reduction for Testing Analog Circuits
Journal of Electronic Testing: Theory and Applications
Op Amps for Everyone
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A BICS for CMOS OpAmps by Monitoring the Supply Current Peak
Journal of Electronic Testing: Theory and Applications
LFSR-based BIST for analog circuits using slope detection
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing
Journal of Electronic Testing: Theory and Applications
Design with Operational Amplifiers and Analog Integrated Circuits
Design with Operational Amplifiers and Analog Integrated Circuits
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A Design of Linearity Built-in Self-Test for Current-Steering DAC
Journal of Electronic Testing: Theory and Applications
On chip testing data converters using static parameters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A comprehensive signature analysis scheme for oscillation-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a digital-compatible testing scheme for operational amplifier (op amp). In the proposed scheme, the op amp device under test (DUT) is configured to a unity-gain buffer which is responded to a testing pulse, could be realized by a ring oscillator circuit. The output of the configured unity-gain buffer is digitized by simple digital counter and then the digitized counting number is compared to a predetermined critical value to evaluate the op amp DUT. The digitized counting number is sensitive to the specification of op amp DUT and easily to be observed in the digital domain. The testing parameters of testing setup of stimulus, testing result, testing accuracy, and testing time are also investigated to detail the proposed scheme. Digital compatibility and simplicity are main advantages of the proposed testing scheme. In addition, no complicated analog comparator and reference voltages are required. Behavioral and circuit level simulations are performed to show the effectiveness of the proposed scheme.