Fault-based testing and diagnosis of balanced filters
Analog Integrated Circuits and Signal Processing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
BIST for D/A and A/D Converters
IEEE Design & Test
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Oscillation-test strategy for analog and mixed-signal integrated circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Frequency-based BIST for analog circuit testing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
Test Evaluation and Data on Defect-Oriented BIST Architecture for High-Speed PLL
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators
Journal of Electronic Testing: Theory and Applications
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Digital-Compatible Testing Scheme for Operational Amplifier
Journal of Electronic Testing: Theory and Applications
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A new digital BIST structure is proposed in this paper. During test mode, the Op Amp under test is placed in a voltage follower configuration in order to detect its slew-rate deviation, or in a comparator configuration in order to detect its signal propagation delay deviation. The test stimuli and the BIST control signals are simply derived from the test control signal TST using delay elements and logical gates. The test response is analyzed by using a pure digital circuitry. Simulation results show the effectiveness of the proposed technique with a low area overhead.