Signals & systems (2nd ed.)
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Analog Testing with Time Response Parameters
IEEE Design & Test
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
On-chip analog output response compaction
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A Test Point Insertion Algorithm for Mixed-Signal Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Testing analog and mixed-signal integrated circuits using oscillation-test method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Signature analysis for analog and mixed-signal circuit test response compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A comprehensive signature analysis scheme for oscillation-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Digital-Compatible Testing Scheme for Operational Amplifier
Journal of Electronic Testing: Theory and Applications
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This paper presents a new analog BIST scheme using a slope detection technique. In test mode, a circuit under test (CUT) is stimulated with a periodic rectangular pulse generated from a Linear Feed-Back Shift Register (LFSR) and a periodic invariant response is generated. The width of the pulse is a BIST parameter to allow a trade-off between test time and fault coverage. In order to maximize fault coverage and minimize the hardware overhead, we propose a slope detection technique which analyzes the response of CUT using a counter and a simple digital gate. Simulation results are presented to show the feasibility of this scheme.