A Signature Analyzer for Analog and Mixed-signal Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Characterization of Floating Gate Defects in Analog Cells
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
IMPLEMENTATION OF MIXED CURRENT/VOLTAGE TESTING USING THE IEEE P1149.4 INFRASTRUCTURE
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Subband Filtering Scheme for Analog and Mixed-Signal Circuit Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
LFSR-based BIST for analog circuits using slope detection
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Oscillation Test Strategy: A Case Study
Journal of Electronic Testing: Theory and Applications
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In this paper, we propose a technique for on-chip analog output response compaction in order to implement self-test capabilities in analog and mixed-signal integrated circuits. The integration function is identified as a powerful analog compression scheme and an analog signature analyzer is proposed. The op amp-based implementation allows one to define single and multiple-input versions. The multiple-input analyzer permits the monitoring of some extra internal nodes in addition to the classical output nodes, or the concurrent control of both voltage and current levels. This ability leads to an improvement of the circuit testability and consequently, the on-chip response evaluation gives a higher fault coverage than the off-chip one.