An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Structure and Metrology for an Analog Testability Bus
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Control and Observation of Analog Nodes in Mixed-Signal Boards
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Structure and Metrology for a Single-wire Analog
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Design for Testability of a Modular, Mixed Signal Family of VLSI Devices
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
On-chip analog output response compaction
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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The development of a mixed-signal test bus infrastructure | IEEE P1149.4 | is now in the final stages ofthe standardization process. Evaluating the test capabilities enabled by this infrastructure is an important stepneeded to support it as a well established standard. Thispaper presents experiments carried out with a test chipprovided by the P1149.4 working group, which explorethe architecture of the proposed analog boundary module to implement alternative testing methods. Theseinclude a method for parametric testing of passive components based on the monitoring of the power supplycurrent, and a mixed current/voltage technique allowing the implementation of correlation for testing analogand mixed-signal macros.