A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Current Testable Design of Resistor String DACs
ATS '07 Proceedings of the 16th Asian Test Symposium
Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
On chip testing data converters using static parameters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Testing flat panel display source driver ICs is a costly process; the root cause is the internal DAC array which is functionally tested. This paper proposes an IDDQ-based design-for-test (DFT) technique to detect the open and short faults inside the DAC array. Compared to previous methods, the proposed DFT technique substantially improves the IDDQ testability and reduces the number of required analog measurements. Spice simulation results are presented to validate the effectiveness of the proposed technique in detecting open and short defects.