A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Linearity Testing Issues of Analog to Digital Converters
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Auto-Calibrating Analog Timer for On-Chip Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A BIST Scheme for SNDR Testing of ΣΔ ADCs Using Sine-Wave Fitting
Journal of Electronic Testing: Theory and Applications
An on-chip solution for static ADC test and measurement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n-bit ADC by using a ramp signal of much less than n-bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses (n + 3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.