Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
An Efficient Scheme to Diagnose Scan Chains
Proceedings of the IEEE International Test Conference
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Quick Scan Chain Diagnosis Using Signal Profiling
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Using fault model relaxation to diagnose real scan chain defects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An algorithmic technique for diagnosis of faulty scan chains
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In scan-based testing environments, identifying the scan chain failures can be of significant help in guiding the failure analysis process for yield improvement. In this paper, we propose an efficient scan chain diagnosis method using a symbolic fault simulation to achieve high diagnostic resolution and small candidate list for single and multiple defects in scan chains. The main ideas of the proposed scan chain diagnosis method are twofold: 1) the reduction of the candidate scan cells through the analysis of the symbolic simulation responses, and 2) the identification of final candidate scan cells using the backward tracing method with the symbolic simulation responses. Experimental results show the effectiveness.