Parallel fault backtracing for calculation of fault coverage

Authors:
Raimund Ubar;Sergei Devadze;Jaan Raik;Artur Jutman
Affiliations:
Tallinn University of Technology, Tallinn, Estonia;Tallinn University of Technology, Tallinn, Estonia;Tallinn University of Technology, Tallinn, Estonia;Tallinn University of Technology, Tallinn, Estonia
Venue:
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Year:
2008

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Abstract

A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults to minimize the repeated calculations because of the reconvergent fanouts. The algorithm is equivalent to exact critical path tracing, however, processing the backtrace in parallel for a group of test patterns. Because of the parallelism, higher abstraction level modeling, and optimization of the topological model, the speed of fault simulation was considerably increased. Compared to the state-of-the-art commercial fault simulators the gain in speed was several times.