Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
Production Experience with Built-In Self-Test in the IBM ES/9000 System
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Improving the efficiency of error identification via signature analysis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Evolving effective CA/CSTP: BIST architectures for sequential circuits
Proceedings of the 2001 ACM symposium on Applied computing
CA-CSTP: A New BIST Architecture for Sequential Circuits
ETW '00 Proceedings of the IEEE European Test Workshop
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Despite all of the advantages that circular BIST offers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern-resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added to system paths. Result indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity.