Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Strongly Fault Secure PLAs and Totally Self-Checking Checkers
IEEE Transactions on Computers
Real-Number Codes for Fault-Tolerant Matrix Operations on Processor Arrays
IEEE Transactions on Computers
Algorithm-Based Fault Detection for Signal Processing Applications
IEEE Transactions on Computers
Multiple fault analog circuit testing by sensitivity analysis
Journal of Electronic Testing: Theory and Applications - Joint special issue on analog and mixed-signal testing
Fault simulation of linear analog circuits
Journal of Electronic Testing: Theory and Applications - Joint special issue on analog and mixed-signal testing
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
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Self-checking in analog circuits is more difficult than in digital circuits. The technique proposed by Abhijit Chatterjee can address concurrent error detection and correction in linear analog circuits and hence the reliability of the original circuit is greatly improved. However, hardware overhead is an important issue in this technique, which has never been addressed before. This paper proposes an algorithm for reduction of hardware overhead in the analog checker, and also presents a serial of theoretic results, including the concept of all-non-zero solutions and several existence conditions of such solutions. As the basis of the algorithm, these results are new in the mathematic world and can be used to verify feasibility and effectiveness of the algorithm. Without changing the original circuit, the proposed algorithm can not only reduce the number of passive elements, but also the number of analog operators so that the error detection circuitry in the checker has optimal hardware overhead.