Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Weighted random test pattern generators: space-time trade-off and evaluation techniques
Weighted random test pattern generators: space-time trade-off and evaluation techniques
A fault simulation method: parallel pattern critical path tracing
Journal of Electronic Testing: Theory and Applications
Structured Logic Testing
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Generation of Optimized Single Distributions of Weights for Random Built-in Self-Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
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In this paper we present a new test per clock BIST technique that provides 100% fault coverage of detectable single stuck-at faults for random pattern resistant circuits with low test application time and limited hardware overhead. The technique uses selective bit-fixing plus biased pseudorandom patterns and is referred to as fixed-biased pseudorandom BIST. An automatic design tool (EBIST) specifies the necessary information for implementation of the BIST hardware. The amount of hardware overhead introduced as controlled by user specified paramefers and can therefore meet varying design specifications. Since the proposed technique relies on bit-fixing, we present a new scan cell which supports bit-fixing. Results are presented for combinational benchmark circuits and comparisons made with prior techniques with respect to test application time and hardware overhead.