Computational Intelligence Characterization Method of Semiconductor Device
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Layout-aware, IR-drop tolerant transition fault pattern generation
Proceedings of the conference on Design, automation and test in Europe
Optimisation of concentrating solar thermal power plants with neural networks
ICANNGA'11 Proceedings of the 10th international conference on Adaptive and natural computing algorithms - Volume Part I
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In our approach, we use ATE (Automatic Test Equipment) to teach a neural network (NN) to correctly classify a set of worst case input pattern with respect to the maximum instantaneous current. This can be thought of as learning a behavior of chip power consumption change due to different input patterns applied. We then further optimize this set of (NN) worst case pattern using genetic algorithm (GA). The final set of worst case pattern can efficiently identify a defective or weakness due to power supply noise as well as locate the defect or weakness within the design. To the best of our knowledge, this is the first NN learning and GA self-optimization ATE-based approach for practical application in silicon analysis automation. Our practical experimental results demonstrate the enlarged fault coverage obtained with this approach.