A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Design for Testability in Nanometer Technologies; Searching for Quality
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Generalized Sensitization using Fault Tuples
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Fault modeling for FinFET circuits
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Testing Partially-Depleted Silicon-On-Insulator (PD-SOI)integrated circuits presents new challenges thatwere not concerns in previous bulk CMOS technologies.Gates are affected by a variation in delay based onthreshold voltage fluctuations. The fluctuations aredependent on the switching history of the device and thisposes a serious challenge with regard to testing delays.To ensure worst-case operation, pre-conditioning of thepath is necessary prior to a delay test. This paperprovides background on SOI device operation anddescribes why and how pre-conditioning is accomplishedIt is shown that a three-pattern delay test where the V1and V3 patterns are the same is required to pre-conditionthe path for worst-case delay. Two novel scan latchdesigns that are capable of applying the three-patterntests are presented.