A simplified six-waveform type method for delay fault testing
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault test generation for scan/hold circuits using Boolean expressions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Scan Latch Design for Delay Test
Proceedings of the IEEE International Test Conference
On Path-Delay Testing in a Standard Scan Environment
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Applying two-pattern tests using scan-mapping
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
This paper describes a test method for analogue (partsof) ICs that determines whether an IC is good or not bymeasuring the currents flowing through its constituent circuits.The ICCQ test method is not a full functional test. Itis aimed primarily ...