A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Hazard-based detection conditions for improved transition fault coverage of scan-based tests
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design-for-testability for multi-cycle broadside tests by holding of state variables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper proposes a new technique, called scan-mapping, for applying two-pattern tests in a standard scan design environment. Scan-mapping is performed by shifting the first pattern (V/sub 1/) into the scan path and then using combinational mapping logic to generate the second pattern (V/sub 2/) in the next clock cycle. The mapping logic is placed in the scan path and avoids the performance degradation of using more complex scan elements to apply two-pattern tests. A procedure is described for synthesizing the mapping logic required to apply a set of two-pattern tests. Scan-mapping can be used in deterministic testing to apply two-pattern tests that can't be applied using scan-shifting or functional justification, and it can be used in built-in self-testing (BlST) to improve the fault coverage for delay faults. Experimental results indicate that, for deterministic testing, scan-mapping can reduce area overhead and test time compared with using complex scan elements; and for pseudo-random testing, scan-mapping can significantly improve the fault coverage using only a small amount of mapping logic.