Efficient path delay test generation based on stuck-at test generation using checker circuitry

Authors:
Tsuyoshi Iwagaki;Satoshi Ohtake;Mineo Kaneko;Hideo Fujiwara
Affiliations:
Japan Advanced Institute of Science and Technology (JAIST), Ishikawa, Japan;Nara Institute of Science and Technology (NAIST), Kansai Science City, Japan;Japan Advanced Institute of Science and Technology (JAIST), Ishikawa, Japan;Nara Institute of Science and Technology (NAIST), Kansai Science City, Japan
Venue:
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Year:
2007

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Abstract

This paper proposes an approach to non-robust and functionally sensitizable path delay test generation through stuck-at test generation. In this approach, to generate two-pattern tests for path delay faults in a combinational circuit, checker circuitry is constructed which is composed of logic gates corresponding to the mandatory assignments for detecting the faults. This checker circuitry allows us to use any existing combinational stuck-at test generation tool. Since today's stuck-at test generation tools reach a mature level, the proposed approach can efficiently solve the path delay test generation problem for combinational circuits. Experimental results show that the approach can speed up path delay test generation and can improve fault efficiency. This paper also discusses how a scan circuit and the issues of over-testing and test power are handled in the proposed test generation framework.