Circuit partitioning for efficient logic BIST synthesis

Pattern generation for a deterministic BIST scheme

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Bit-flipping BIST

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Constructive Multi-Phase Test Point Insertion for Scan-Based BIST

Proceedings of the IEEE International Test Conference on Test and Design Validity

Altering a Pseudo-Random Bit Sequence for Scan-Based BIST

Proceedings of the IEEE International Test Conference on Test and Design Validity

Using BIST Control for Pattern Generation

Proceedings of the IEEE International Test Conference

Deterministic BIST with multiple scan chains

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Testing embedded-core based system chips

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Deterministic BIST with Partial Scan

ETW '99 Proceedings of the 1999 IEEE European Test Workshop

Test generation costs analysis and projections

DAC '80 Proceedings of the 17th Design Automation Conference

Test generation for large logic networks

DAC '77 Proceedings of the 14th Design Automation Conference

Application of Deterministic Logic BIST on Industrial Circuits

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Logic BIST for Large Industrial Designs: Real Issues and Case Studies

ITC '99 Proceedings of the 1999 IEEE International Test Conference

AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS

DAC '78 Proceedings of the 15th Design Automation Conference