High-Frequency, At-Speed Scan Testing
IEEE Design & Test
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
Proceedings of the Conference on Design, Automation and Test in Europe
Deterministic test for the reproduction and detection of board-level functional failures
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A physical-location-aware X-bit redistribution for maximum IR-drop reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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For years, there has been a ongoing debate in the industry regarding the effectiveness and costs associated with functional versus DFT-oriented testing and ATE. To answer important questions that arise from the functional vs. DFT debate, we consider actual production dataanalysis to evaluate the value of functional and DFT tests. Production test data from 10,000 parts randomly sampled from over 1 million total datalogs of the Motorola MPC7410 microprocessor, a high-volume design, is used to evaluate the value of ATE features in terms of test escape rates across different tests. We also examine the value of features that cannot necessarily be quantified in terms of test escape rates. This work will help to provide some insight into how to lower the cost of test by making the right tradeoffs in terms of ATE features without compromising overall test coverage and quality.