Soft error-aware design optimization of low power and time-constrained embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study
Microprocessors & Microsystems
Facilitating the design of fault tolerance in transaction level systemc programs
ICDCN'12 Proceedings of the 13th international conference on Distributed Computing and Networking
Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation
Microprocessors & Microsystems
Facilitating the design of fault tolerance in transaction level SystemC programs
Theoretical Computer Science
Journal of Systems and Software
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In this paper, we propose a new SystemC-based fault injection technique that has improved fault representation in visible and on-the-fly data and signal registers. The technique is minimum intrusive since it only requires replacing the original data or signal types to fault injection enabler types. We compare the proposed simulation technique with recently reported SystemC-based techniques and show that our technique has fast simulation speed, better fault representation, while maintaining simplicity and minimum intrusion. We demonstrate fault injection capabilities in a behavioural SystemC description of MPEG-2 decoder using proposed technique and show that up to 98.9% fault representation within data and signal registers can be achieved.