The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
System Design with SystemC
AspectC++: an aspect-oriented extension to the C++ programming language
CRPIT '02 Proceedings of the Fortieth International Conference on Tools Pacific: Objects for internet, mobile and embedded applications
ECOOP '01 Proceedings of the 15th European Conference on Object-Oriented Programming
Aspect-oriented design in systemC: implementation and applications
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Verification methodologies in a TLM-to-RTL design flow
Proceedings of the 44th annual Design Automation Conference
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
A fine-grained join point model for more reusable aspects
APLAS'06 Proceedings of the 4th Asian conference on Programming Languages and Systems
ASystemC: an AOP extension for hardware description language
Proceedings of the tenth international conference on Aspect-oriented software development companion
| Hi-index | 0.00 |
Verifying very-large-scale integration (VLSI) circuit design using assertions is becoming more common. Herein, an assertion represents a temporal relationship among circuit events over time using temporal logic expression. On the other hand, "high-level design" has also become more common recently. Instead of conventional hardware description languages (HDLs), VLSI designers introduce C-based design languages. Although both of these trends are fairly effective in VLSI development, there is a big gap between these two approaches. Since conventional assertion languages are for conventional HDLs, they only allow specification of change of variables or low-level events raised along with signals. In high-level design, however, there are various high-level events, such as a method call or a state transition which no conventional assertion language can handle. This paper proposes a new assertion language extension, namely, a pointcut-based assertion that enhances an existing assertion language to make assertions available even in high-level design. We introduce a pointcut notion to specify various events from low-level signal-related ones to high-level state transition-related ones. To conduct proof-of-concept, we designed and implemented two assertion languages with pointcut-based assertions, called ASystemC and ASpecC. ASystemC uses the pointcut expressions in AspectC++, and the implementation also uses the AspectC++ compiler as its back-end. We present feasibility and preliminary evaluation of our approach with ASystemC. ASpecC is designed with practical use in mind and based on the continuation join point model with slight modification to support hardware-specific matters. We show that the model is useful for making pointcut-based assertion more robust.