Fault models and test generation for hardware-software covalidation

Authors:
I. G. Harris
Affiliations:
California Univ., Irvine, CA, USA
Venue:
IEEE Design & Test
Year:
2003

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Facilitating the design of fault tolerance in transaction level SystemC programs

Theoretical Computer Science

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Abstract

Mixed hardware-software systems constitute a strong paradigm shift for system validation. The main barriers to overcome are finding the right fault models and optimizing the validation flow. This article presents a research summary of these issues.