A refinement calculus for the synthesis of verified hardware descriptions in VHDL
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal specification in VHDL for hardware verification
Proceedings of the conference on Design, automation and test in Europe
Denotational semantics of a behavioral subset of VHDL
Proceedings of the conference on Design, automation and test in Europe
Formal Semantics of Synchronous SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Evaluating possibilities for formally sound simulation and verification of VHDL
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
A logic to specify and verify synchronous transitions
IW-FM'99 Proceedings of the 3rd Irish conference on Formal Methods
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