Denotational semantics of a behavioral subset of VHDL

Authors:
F. Nicoli
Affiliations:
LIM - ESA 6077, CMI - Université de Provence, 39, rue Joliot-Curie, 13453 Marseille - France
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

Citing 4
Cited 0

A computational logic handbook

A computational logic handbook
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Semantics of a verification-oriented subset of VHDL

CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

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Abstract

This paper introduces a denotational semantics of a behavioral subset of VHDL. This subset is restricted to basic data types only and does not allow for clauses in wait statement. We consider the full model of time and resolution, we give a precise definition of the simulation mechanism. Easy translation rules from VHDL to Boyer-Moore logic can be derived from that semantics.