Reasoning about VHDL and VHDL-AMS using denotational semantics
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Structural Operational Semantics for a Portable Subset of Behavioral VHDL-93
Formal Methods in System Design
Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Information flow analysis for VHDL
PaCT'05 Proceedings of the 8th international conference on Parallel Computing Technologies
Evaluating possibilities for formally sound simulation and verification of VHDL
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
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