A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Formal Synthesis at the Algorithmic Level
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A constructive approach towards correctness of synthesis-application within retiming
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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