Data structures and network algorithms
Data structures and network algorithms
Automata for modeling real-time systems
Proceedings of the seventeenth international colloquium on Automata, languages and programming
HSIS: a BDD-based environment for formal verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
An iterative approach to verification of real-time systems
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
Iterative methods for formal verification of digital systems
Iterative methods for formal verification of digital systems
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Timing Verification by Successive Approximation
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Suspension Automata: A Decidable Class of Hybrid Automata
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
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Most embedded real-time systems consist of many concurrent components operating at significantly different speeds. Thus, an algorithm for formal verification of such systems must efficiently deal with a large number of states and large ratios of timing constants. We present such an algorithm based on timed automata, a model where a finite state system is augmented with time measuring devices called timers. We also present a semi-decision procedure for an extended model where timers can be decremented. This extension allows describing behaviors that are not expressible by timed automata, for example interrupts in a real-time operating system.