Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Modalities for model checking: branching time logic strikes back
Science of Computer Programming
Analysis of discrete event coordination
REX workshop Proceedings on Stepwise refinement of distributed systems: models, formalisms, correctness
Handbook of theoretical computer science (vol. B)
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Efficient omega-Regular Language Containment
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Incremental formal design verification
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
HSIS: a BDD-based environment for formal verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
Formal Methods in System Design
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