Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
Computer-aided prediction of delays in LSI logic systems
DAC '73 Proceedings of the 10th Design Automation Workshop
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
PERT as an aid to logic design
IBM Journal of Research and Development
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This paper presents a static timing analyzer for flexible TFT circuits (STAF). Gate delay models are first characterized by SPICE simulation as a function of load capacitance and mobility. A block-based STA algorithm is then applied to identify the longest path delay and shortest path delay change in different regions under bending. STAF plots maps that show "bending hot spots" which, when bended, significantly change the circuit timing. Experimental results on ISCAS'89 benchmark circuits show that the longest path delay can increase by up to 32% when a single region is bended. What is worse, the shortest path change can be up to 9%, which cannot be simply fixed by reduced clock speed. STAF provides important timing information for flexible TFT circuit designers.