Introduction to VLSI Systems
SCALD: Structured Computer-Aided Logic Design
DAC '78 Proceedings of the 15th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Design integrity and immunity checking: A new look at layout verification and design rule checking
DAC '80 Proceedings of the 17th Design Automation Conference
Bristle Blocks: A silicon compiler
DAC '79 Proceedings of the 16th Design Automation Conference
Understanding hierarchical design
Understanding hierarchical design
Programming aspects of VLSI: (preliminary version)
POPL '82 Proceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Hierarchical layout verification
DAC '84 Proceedings of the 21st Design Automation Conference
| Hi-index | 0.00 |
An extension to a language-based custom VLSI design approach is proposed in which the designer supplies just enough up-front semantic information to allow a substantial amount of beneficial design consistency checking with a minimum of computation. The computational load is reduced by using a bottom-up hierarchical design approach, with incremental checking as the design is built. The load is also reduced by imposing minor restrictions upon the layout designer, by requiring that all active elements be prechecked, and by attaching “type” attributes to interconnecting signals. The method is very efficient for highly “regular” designs. Checks performed are geometrical design rules, connectivity, static electrical consistency, and node rise-and-fall times.