Formal verification of a SHA-1 circuit core using ACL2

Authors:
Diana Toma;Dominique Borrione
Affiliations:
TIMA Laboratory, VDS Group, Grenoble, France;TIMA Laboratory, VDS Group, Grenoble, France
Venue:
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
Year:
2005

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Abstract

Our study was part of a project aiming at the design and verification of a circuit for secure communications between a computer and a terminal smart card reader. A SHA-1 component is included in the circuit. SHA-1 is a cryptographic primive that produces, for any message, a 160 bit message digest. We formalize the standard specification in ACL2, then automatically produce the ACL2 model for the VHDL RTL design; finally, we prove the implementation compliant with the specification. We apply a stepwise approach that proves theorems about each computation step of the RTL design, using intermediate digest functions.