Verifying properties of hardware and software by predicate abstraction and model checking

Authors:
R. E. Bryant;S. K. Rajamani
Affiliations:
Carnegie Mellon Univ., Pittsburgh, PA, USA;Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

Citing 5
Cited 0

Automatically validating temporal safety properties of interfaces

SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
The SLAM project: debugging system software via static analysis

POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Construction of Abstract State Graphs with PVS

CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Modeling and Verifying Systems Using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions

CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic abstraction and verification of verilog models

Proceedings of the 41st annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

This tutorial describes automatic techniques for formally verifying hardware and software by creating Boolean abstractions of the underlying unbounded system state variables.