Journal of Symbolic Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Modeling and querying biomolecular interaction networks
Theoretical Computer Science - Special issue: Computational systems biology
Counting truth assignments of formulas of bounded tree-width or clique-width
Discrete Applied Mathematics
Treewidth in verification: local vs. global
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Using DPLL for efficient OBDD construction
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Machine learning biochemical networks from temporal logic properties
Transactions on Computational Systems Biology VI
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In this paper, we propose cutwidth based heuristics to improve the efficiency of symbolic simulation and SAT algorithms. These algorithms are the underlying engines of many formal verification techniques. We present a new approach for computing variable orderings that reduce CNF/circuit cutwidth. We show that the circuit cutwidth and the peak number of live BDDs during symbolic simulation are equal. Thus using an ordering that reduces the cutwidth in scheduling the gates during symbolic simulation can significantly improve both the runtime and memory requirements. It has been shown that the time complexity of SAT problems can be bounded exponentially by the formula cutwidth and many practical circuits has cutwidth logarithmic of the size of the formulas. We have developed cutwidth based heuristics which in practice can speed up existing SAT algorithms, especially for SAT instances with small cutwidth. We demonstrate the power of our approach on a number of standard benchmarks.