Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
A partial approach to model checking
Papers presented at the IEEE symposium on Logic in computer science
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
Symbolic Model Checking
Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem
An improvement in formal verification
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Formal Verification of a Partial-Order Reduction Technique for Model Checking
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
All from One, One for All: on Model Checking Using Representatives
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Linear Time, Branching Time and Partial Order in Logics and Models for Concurrency, School/Workshop
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Preventing race condition attacks on file-systems
Proceedings of the 2005 ACM symposium on Applied computing
Automated Online Monitoring of Distributed Applications through External Monitors
IEEE Transactions on Dependable and Secure Computing
Exploiting interleaving semantics in symbolic state-space generation
Formal Methods in System Design
Formal Sequentialization of Distributed Systems via Program Rewriting
Electronic Notes in Theoretical Computer Science (ENTCS)
The Design of a Multicore Extension of the SPIN Model Checker
IEEE Transactions on Software Engineering
Survey on Directed Model Checking
Model Checking and Artificial Intelligence
Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Partial Order Reduction for Probabilistic Systems: A Revision for Distributed Schedulers
CONCUR 2009 Proceedings of the 20th International Conference on Concurrency Theory
Specification Languages for Stutter-Invariant Regular Properties
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
A component-based approach to verification and validation of formal software models
Architecting dependable systems IV
Peephole partial order reduction
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
SMT-based bounded model checking for multi-threaded software in embedded systems
Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering - Volume 2
Boosting lazy abstraction for systemc with partial order reduction
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Symbolic model checking of concurrent programs using partial orders and on-the-fly transactions
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Symbolic model checking for asynchronous boolean programs
SPIN'05 Proceedings of the 12th international conference on Model Checking Software
Compositional model extraction for higher-order concurrent programs
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Supporting domain-specific state space reductions through local partial-order reduction
ASE '11 Proceedings of the 2011 26th IEEE/ACM International Conference on Automated Software Engineering
A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 2012 Extreme Modeling Workshop
Hi-index | 0.00 |
State-space explosion is a fundamental obstacle in the formal verification of designs and protocols. Several techniques for combating this problem have emerged in the past few years, among which two are significant: partial-order reduction and symbolic state-space search. In asynchronous systems, interleavings of independent concurrent events are equivalent, and only a representative interleaving needs to be explored to verify local properties. Partial-order methods exploit this redundancy and visit only a subset of the reachable states. Symbolic techniques, on the other hand, capture the transition relation of a system and the set of reachable states as boolean functions. In many cases, these functions can be represented compactly using binary decision diagrams (BDDs). Traditionally, the two techniques have been practiced by two different schools—partial-order methods with enumerative depth-first search for the analysis of asynchronous network protocols, and symbolic breadth-first search for the analysis of synchronous hardware designs. We combine both approaches and develop a method for using partial-order reduction techniques in symbolic BDD-based invariant checking. We present theoretical results to prove the correctness of the method, and experimental results to demonstrate its efficacy.