Programming in Occam
Theoretical Computer Science
Design and validation of computer protocols
Design and validation of computer protocols
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
Formal Methods in System Design - Special issue on The First Federated Logic Conference (FLOC'96), part II
Model checking
Partial-Order Reduction in Symbolic State-Space Exploration
Formal Methods in System Design - Special issue on CAV '97
Concurrency verification: introduction to compositional and noncompositional methods
Concurrency verification: introduction to compositional and noncompositional methods
Symbolic Model Checking
Static Partial Order Reduction
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Static Analysis for State-Space Reductions Preserving Temporal Logics
Formal Methods in System Design
An Input/Output Semantics for Distributed Program Equivalence Reasoning
Electronic Notes in Theoretical Computer Science (ENTCS)
A static communication elimination algorithm for distributed system verification
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
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Formal sequentialization is introduced as a rewriting process for the reduction of parallelism and internal communication statements of distributed imperative programs. It constructs an equivalence proof in an implicit way, via the application of equivalence laws as rewrite rules, thus generating a chain of equivalent programs. The variety of the possible sequentialization degrees which are attainable is illustrated with an example. The approach is static, thus avoiding the state explosion problem, has an impressive state-vector reduction in many cases, and could be combined, as a model simplification step, with model checking and interactive theorem proving in system verification. Prior grounding results needed in formal sequentialization are overviewed; more specifically, an algorithm for the automatic elimination of communications under the scope of sequential and parallel compositions, elimination laws which the algorithm applies, and a suitable equivalence criterion for the sequentialization process. The main contribution of this work is the extension of these results to encompass the formal elimination of both synchronous communications embedded within a subclass of selection statements, and of non-disjoint synchronous communication pairs. None of these cases has been treated in the literature before, and their solution considerably widens the application domain of formal sequentialization.