Programming in Occam
Theoretical Computer Science
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Design and validation of computer protocols
Design and validation of computer protocols
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
An Industrial Strength Theorem Prover for a Logic Based on Common Lisp
IEEE Transactions on Software Engineering
Model checking
Verifying Temporal Properties of Reactive Systems: A STeP Tutorial
Formal Methods in System Design
Concurrency verification: introduction to compositional and noncompositional methods
Concurrency verification: introduction to compositional and noncompositional methods
Symbolic Model Checking
Formal Sequentialization of Distributed Systems via Program Rewriting
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic mining of functionally equivalent code fragments via random testing
Proceedings of the eighteenth international symposium on Software testing and analysis
A static communication elimination algorithm for distributed system verification
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
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A new notion of input/output equivalence of distributed imperative programs, with synchronous communications, is introduced. It preserves the input/output relation, encompassing both, initial/final state and communication channel values. For its mathematical justification, the semantic framework of Manna and Pnueli, based on finite transition systems and reduced behaviors, is extended with the notion of input/output behavior. A set of laws for the equivalence is overviewed. A deduction rule for the substitution of references to input/output equivalent procedures is defined and justified in the new semantics. The rule is applied to decompose distributed program simplification proofs, introduced in a prior work, which use the laws to establish the equivalence between a sequential and a parallel communicating program. They include communication elimination as one of their steps. An outline of one of such proofs, for a pipelined processor model, is included.