Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Verifying the summit bus converter protocols with symbolic model checking
Formal Methods in System Design
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Symbolic Model Checking is one of the most efficient formal verification methods for hardware design. It uses Computational Tree Logic (CTL) for expressing formal specification of hardware design. However, the large demands of space by Symbolic Model Checking prevents itself from verifying large automates. In this paper we study the possibility of hierarchy evaluation of CTL formula. The result shows that CTL specifications for whole automata can be decomposed into local properties in some case, each of them can be verified on different subautomates respectively. By this way symbolic model checking can be completed hierarchically, which enable us to handle much larger circuits without a large growth of complexity.