Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
ACV: an arithmetic circuit verifier
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
MORE: an alternative implementation of BDD packages by multi-operand synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Dynamic minimization of OKFDDs
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Implementation of a multiple-domain decision diagram package
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Automatic Datapath Extraction for Efficient Usage of HDD
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Formal verification of word-level specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Verifying integrity of decision diagrams
Integration, the VLSI Journal
Minimization of word-level decision diagrams
Integration, the VLSI Journal
Verifying Integrity of Decision Diagrams
SAFECOMP '98 Proceedings of the 17th International Conference on Computer Safety, Reliability and Security
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
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Word-Level Decision Diagrams (WLDDs), like *BMDs and K*BMDs, have recently been introduced as a data structure for verification. The size of WLDDs largely depends on the chosen variable ordering, i.e. the ordering in which variables are encountered, and on the decompositions carried out in each node. In this paper we present a framework for dynamic minimization of WLDDs. We discuss the difficulties with previous techniques if applied to WLDDs and present a new approach that efficiently adapts both variable ordering and decomposition type choice. Experimental results demonstrate that this method outperforms ``classical'' reordering with respect to run-time and representation size during dynamic minimization of word-level functions.