Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
DAC '94 Proceedings of the 31st annual Design Automation Conference
Two-level logic minimization: an overview
Integration, the VLSI Journal
Functional multiple-output decomposition: theory and an implicit algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Implementation of an efficient parallel BDD package
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dynamic minimization of word-level decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Multi-output functional decomposition with exploitation of don't cares
Proceedings of the conference on Design, automation and test in Europe
Dynamic minimization of OKFDDs
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Implementation of a multiple-domain decision diagram package
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Checking the Integrity of Trees
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
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Decision Diagrams (DDs) are the state-of-the-art data structure in CAD of integrated circuits. They are used in many safety critical applications, like verification. In this paper security aspects of implementation techniques of DDs are discussed. A recursive checksum technique is presented for on-line and off-line checks. These methods are used to verify the integrity of DDs. The correctness of the data structures can be verified by (nearly) no overhead. Experimental results are presented to demonstrate the efficiency of this approach.