Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
On the effect of local changes in the variable ordering of ordered decision diagrams
Information Processing Letters
Fast OFDD-Based Minimization of Fixed Polarity Reed-Muller Expressions
IEEE Transactions on Computers
ACV: an arithmetic circuit verifier
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Interleaving based variable ordering methods for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On Variable Ordering and Decomposition Type Choice in OKFDDs
IEEE Transactions on Computers
Using lower bounds during dynamic BDD minimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dynamic minimization of word-level decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Factored Edge-Valued Binary Decision Diagrams
Formal Methods in System Design
The K*BMD: A Verification Data Structure
IEEE Design & Test
BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Implementation of a multiple-domain decision diagram package
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Automatic Datapath Extraction for Efficient Usage of HDD
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
Fast functional evaluation of candidate OBDD variable orderings
EURO-DAC '91 Proceedings of the conference on European design automation
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDD minimization using symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Word-Level Decision Diagrams (WLDDs), like *BMDs and K*BMDs, have recently been introduced as a data structure for verification. The size of WLDDs largely depends on the chosen variable ordering, i.e. the ordering in which variables are encountered, on the decompositions carried out in each node, and on the grouping of the outputs.In this paper we present a framework for dynamic minimization of WLDDs by changing the ordering and the decomposition type. We discuss the difficulties with previous techniques if applied to WLDDs and present a new approach that efficiently adapts both, variable ordering and decomposition type choice. Furthermore, we present a technique that is based on computing lower bounds to speed up dynamic minimization. Finally, for output grouping a first heuristic is presented that groups the outputs based on information extracted from the circuit topology. For all approaches experimental results are given that show the efficiency of the techniques proposed.