Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Field-programmable gate arrays
Field-programmable gate arrays
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Reduction of OBDDs in linear time
Information Processing Letters
Boolean matching using generalized Reed-Muller forms
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Fast Minimization of Mixed-Polarity AND/XOR Canonical Networks
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Minimization of word-level decision diagrams
Integration, the VLSI Journal
RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 14.98 |
We present methods to minimize fixed polarity Reed-Muller expressions (FPRMs), i.e., two-level fixed polarity AND/EXOR canonical representations of Boolean functions, using ordered functional decision diagrams (OFDDs). We investigate the close relation between both representations and use efficient algorithms on OFDDs for exact and heuristic minimization of FPRMs. In contrast to previously published methods, our algorithm can also handle circuits with several outputs. Experimental results on large benchmarks are given to show the efficiency of our approach.