Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Evaluating Symbolic Traversal Algorithms Applied to Asynchronous Concurrent Systems
ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
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transyt is a BDD-based tool specifically designed for the verification of timed and untimed asynchronous concurrent systems. transyt system architecture is designed to be modular, open and flexible, such that additional capabilities can be easily integrated. A state of the art BDD package [1] is integrated into the system, and a middleware extension [2] provides support complex BDD manipulation strategies.