Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
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We propose a novel approach to transform an arbitrary Mealy machine, which is a kind of Finite State Machine (FSM) with outputs, into so-called Linear Binary Moment Diagrams (LBMDs).We stress the attractive features of this approach, and demonstrate the results of experiments on benchmarks in comparison with a state-of-the art Reduced Ordered Binary Decision Diagrams technique.