VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
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Model checking is a promising formal verification technique successfully applied in several industrial environments, such as in chip design and in the telecommunication industry. In this paper, preliminary results of an automotive case study are presented as performed in the context of the European project EASIS.