The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
A methodology for hardware verification using compositional model checking
Science of Computer Programming - Special issue on mathematics of program construction
LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
FASE '02 Proceedings of the 5th International Conference on Fundamental Approaches to Software Engineering
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
vUML: A Tool for Verifying UML Models
ASE '99 Proceedings of the 14th IEEE international conference on Automated software engineering
The Rhapsody UML Verification Environment
SEFM '04 Proceedings of the Software Engineering and Formal Methods, Second International Conference
Integration of model checking into software development processes
Integration of model checking into software development processes
A discrete-time UML semantics for concurrency and communication in safety-critical applications
Science of Computer Programming - Formal methods for components and objects pragmatic aspects and applications
Live and let die: LSC based verification of UML models
Science of Computer Programming - Formal methods for components and objects pragmatic aspects and applications
Counterexample Guided Spotlight Abstraction Refinement
FORTE '08 Proceedings of the 28th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Non-interference properties for data-type reduction of communicating systems
IFM'07 Proceedings of the 6th international conference on Integrated formal methods
Mind the shapes: abstraction refinement via topology invariants
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Check it out: on the efficient formal verification of live sequence charts
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Efficient probabilistic abstraction for SysML activity diagrams
SEFM'12 Proceedings of the 10th international conference on Software Engineering and Formal Methods
Scenario-driven analysis of systems specified through graph transformations
Journal of Visual Languages and Computing
A property-based abstraction framework for SysML activity diagrams
Knowledge-Based Systems
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The approaches to automatic formal verification of UML models known up to now require a finite bound on the number of objects existing at each point in time. In [W. Damm, B. Westphal, Live and let die: LSC-based verification of UML-models, Science of of Computer Programming 55 (2005) 117-159] we have observed that the class of hardware systems with replicated components studied by McMillan [K.L. McMillan, A methodology for hardware verification using compositional model checking, Science of Computer Programming 37 (2000) 279-309] is equivalent to the class of systems where the only source of infiniteness is unbounded creation and destruction of objects, i.e. where all data-types except for object identities are finite. Exploiting the symmetry of UML models induced by objects being instances of classes, the restriction to finite bounds can be overcome applying [K.L. McMillan, A methodology for hardware verification using compositional model checking, Science of Computer Programming 37 (2000) 279-309]. In this paper we report on experiences from an evaluation of this approach within the UML Verifi- cation Environment (UVE) [I. Schinz, T. Toben, C. Mrugalla and B. Westphal, The Rhapsody UML Verification Environment, in: J.R. Cuellar and Z. Liu, editors, Proceedings SEFM 2004 (2004), pp. 174-183], a state-of-the-art tool for formal verification of UML models using Live Sequence Charts (LSC) [W. Damm, D. Harel, LSCs: Breathing Life into Message Sequence Charts, Formal Methods in System Design 19 (2001) 45-80] for requirements specification.