Assert and negate revisited: modal semantics for UML sequence diagrams
Proceedings of the 2006 international workshop on Scenarios and state machines: models, algorithms, and tools
Modelling and model checking suspendible business processes via statechart diagrams and CSP
Science of Computer Programming
Verification and Synthesis of OCL Constraints Via Topology Analysis
Applications of Graph Transformations with Industrial Relevance
Assessing Modal Aspects of OntoUML Conceptual Models in Alloy
ER '09 Proceedings of the ER 2009 Workshops (CoMoL, ETheCoM, FP-UML, MOST-ONISW, QoIS, RIGiM, SeCoGIS) on Advances in Conceptual Modeling - Challenging Perspectives
LSC Verification for UML Models with Unbounded Creation and Destruction
Electronic Notes in Theoretical Computer Science (ENTCS)
From model-based design to formal verification of adaptive embedded systems
ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
On the expressive power of live sequence charts
Program analysis and compilation, theory and practice
Some results on the expressive power and complexity of LSCs
Pillars of computer science
A state/event-based model-checking approach for the analysis of abstract system properties
Science of Computer Programming
MBEERTS'07 Proceedings of the 2007 International Dagstuhl conference on Model-based engineering of embedded real-time systems
Scenario-based verification of real-time systems using Uppaal
Formal Methods in System Design
A framework for reviewing domain specific conceptual models
Computer Standards & Interfaces
Check it out: on the efficient formal verification of live sequence charts
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Synthesis revisited: generating statechart models from scenario-based requirements
Formal Methods in Software and Systems Modeling
The good, the bad and the ugly: well-formedness of live sequence charts
FASE'06 Proceedings of the 9th international conference on Fundamental Approaches to Software Engineering
Specifying UML protocol state machines in alloy
IFM'12 Proceedings of the 9th international conference on Integrated Formal Methods
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Object-oriented modeling plays an increasing role in the design of embedded controllers.Formal verification can be applied in order to give evidence for meeting safety critical requirements.The "Rhapsody UML Verification Environment" supports verification of safety and liveness requirements for embedded controllers, developed within the Unified Modeling Language (UML).The verification environment is integrated in the design tool "Rhapsody in C++" offered by the company I-Logix. This paper discusses how UML models are transformed into a format usable for the VIS model checker, shows the specification and verification on a simple example and explains how the tool can be used to help determining the memory resources of a model.